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november 2006 rev 3 1/70 70 L6714 4 phase controller with embedded drivers for intel vr10, vr11 and amd 6bit cpus features 0.5% output voltage accuracy 7/8 bit programmable output up to 1.60000v - intel vr10.x, vr11 dac 6 bit programmable output up to 1.5500v - amd 6bit dac high current integrated gate drivers full differential cu rrent sensing across inductor or low side mosfet embedded vrd thermal monitor integrated remote sense buffer dynamic vid management adjustable reference voltage offset programmable soft-start low-side-less startup programmable over voltage protection preliminary over voltage constant over current protection oscillator internally fixe d at 150khz externally adjustable output enable ss_end / pgood signal tqfp64 10mm x 10mm package with exposed pad application high current vrd for desktop cpus workstation and serv er cpu power supply vrm modules description L6714 implements a four phase step-down controller with 90o phase-shift between each phase with integrated high current drivers in a compact 10mm x 10mm body package with exposed pad. the device embeds selectable dacs: the output voltage ranges up to 1.60000v (both intel vr10.x and vr11 dac) or up to 1.5500v (amd 6bit dac) managing d-vid with 0.5% output voltage accuracy over line and temperature variations. additional programmable offset can be added to the reference voltage with a single external resistor. the controller assures fast protection against load over current and under / over voltage (in this last case also before uvlo). in case of over-current the system works in constant current mode until uvp. selectable current reading adds flexibility to the design allowing current sense across inductor or ls mosfet. system thermal monitor is also provided allowing system protection from over-temperature conditions. tqfp64 (exposed pad) www.st.com order codes part number package packaging L6714 tqfp64 tube L6714tr tqfp64 tape and reel
contents L6714 2/70 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 vid tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 mapping for the intel vr11 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 voltage identification (vid) for intel vr11 mode . . . . . . . . . . . . . . . . . . . 17 5.3 voltage identifications (vid) for intel vr10 mode + 6.25mv . . . . . . . . . . 19 5.4 mapping for the amd 6bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 voltage identifications (vid ) codes for amd 6bit mode . . . . . . . . . . . . . 21 6 reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 configuring the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 dac selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 current reading and current shari ng loop . . . . . . . . . . . . . . . . . . . . . . 32 10.1 low side current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2 inductor current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11 remote voltage sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
L6714 contents 3/70 12 voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.1 droop function (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.2 offset (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 dynamic vid transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15 soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 15.1 intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.2 amd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.3 low-side-less startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16 output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . 47 16.1 under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.2 preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.3 over voltage and programmable ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 16.4 pgood (only for amd mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 17 maximum duty-cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 18 over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 18.1 low side mosfet sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 18.2 inductor sense over current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 19 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 20 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21 system control loop compensati on . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 21.1 compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 22 thermal monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
contents L6714 4/70 23 tolerance band (tob) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 23.1 controller tolerance (tob controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 23.2 ext. current sense circuit tolerance (tob currsense - inductor sense) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 23.3 time constant matching error tolerance (tob tcmatching) . . . . . . . . . . 63 23.4 temperature measurement error (vtc) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 24 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.1 power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.2 small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 65 25 embedding L6714 - based vr... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 26 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 27 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
L6714 block diagram 5/70 1 block diagram figure 1. L6714 block diagram logic pwm adaptive anti cross conduction logic pwm adaptive anti cross conduction logic pwm adaptive anti cross conduction hs1 hs1 hs2 ls2 hs3 ls3 boot1 ugate1 phase1 vccdr1 lgate1 pgnd1 boot2 ugate2 phase2 vccdr2 lgate2 pgnd2 boot3 ugate3 phase3 vccdr3 lgate3 pgnd3 current sharing correction 4 phase oscillator ch2 current reading ch3 current reading ch4 current reading ocp4 ocp3 ocp2 L6714 control logic and protections pwm1 pwm2 pwm3 pwm1 pwm2 pwm3 ocp1 ocp3 ocp4 ocp2 digital soft start offset dac with dynamic vid control cs2- cs2+ cs3- cs3+ cs4- cs4+ sgnd vcc outen osc / fault outen vid0 vid1 vid2 vid3 vid4 vid5 vid6 dac/cs_sel outen vcc 1.240v vsen fbr fbg ovp comparator +150mv / 1.800v / ovp 64k 64k 64k 64k remote buffer average current current sharing correction current sharing correction logic pwm adaptive anti cross conduction hs4 ls4 boot4 ugate4 phase4 vccdr4 lgate4 pgnd4 pwm4 current sharing correction ch1 current reading ocp1 cs1- cs1+ pwm4 total delivered current offset vid_sel vccdr ss_osc / ref vid7 / d-vid cs_sel cs_sel ss_end / pgood vr_hot vr_fan tm 3.600v 3.200v vcc cs_sel cs_sel cs_sel ovp 12.5 a ovp dac / cs_sel 12.5 a dac / cs_sel i droop i offset droop comp error amplifier fb i offset
pin settings L6714 6/70 2 pin settings 2.1 connections figure 2. pin connection (through top view) 60 59 58 57 56 55 54 53 52 51 50 49 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 123456789101112 droop fb comp cs4+ cs4- cs2+ cs2- cs3+ cs3- cs1+ cs1- offset pgnd1 pgnd3 lgate3 vccdr3 vccdr2 lgate2 pgnd2 pgnd4 lgate4 vccdr4 sgnd tm vr_fan vr_hot ss_end / pgood vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 / d-vid osc / fault uagte1 boot1 n.c. phase3 ugate3 boot3 n.c. phase2 ugate2 boot2 n.c. phase4 L6714 fbg fbr vid_sel ovp 36 35 34 33 17 18 19 20 outen ssosc / ref sgnd vsen 13 14 15 16 ugate4 boot4 dac / cs_sel vcc 64 63 62 61 n.c. phase1 vccdr1 lgate1
L6714 pin settings 7/70 2.2 functions table 1. pin functions n pin function 1ugate1 channel 1 hs driver output. a small series resistors helps in reducing device-dissipated power. 2boot1 channel 1 hs driver supply. connect through a capacitor (100nf typ.) to phase1 and provide necessary bootstrap diode. a small resistor in series to the boot diode helps in reducing boot capacitor overcharge. 3 n.c. not internally connected. 4 phase3 channel 3 hs driver return path. it must be connected to the hs3 mosfet source and provides return path for the hs driver of channel 3. 5ugate3 channel 3 hs driver output. a small series resistors helps in reducing device-dissipated power. 6boot3 channel 3 hs driver supply. connect through a capacitor (100nf typ.) to phase3 and provide necessary bootstrap diode. a small resistor in series to the boot diode helps in reducing boot capacitor overcharge. 7 n.c. not internally connected. 8 phase2 channel 2 hs driver return path. it must be connected to the hs2 mosfet source and provides return path for the hs driver of channel 2. 9ugate2 channel 2 hs driver output. a small series resistors helps in reducing device-dissipated power. 10 boot2 channel 2 hs driver supply. connect through a capacitor (100nf typ.) to phase2 and provide necessary bootstrap diode. a small resistor in series to the boot diode helps in reducing boot capacitor overcharge. 11 n.c. not internally connected. 12 phase4 channel 4 hs driver return path. it must be connected to the hs4 mosfet source and provides return path for the hs driver of channel 4. 13 ugate4 channel 4 hs driver output. a small series resistors helps in reducing device-dissipated power. 14 boot4 channel 4 hs driver supply. connect through a capacitor (100nf typ.) to phase4 and provide necessary bootstrap diode. a small resistor in series to the boot diode helps in reducing boot capacitor overcharge.
pin settings L6714 8/70 15 vcc device supply voltage. the operative voltage is 12v 15%. filter with 1f (typ) mlcc vs. sgnd. 16 dac/ cs_sel dac and c urrent s ense sel ection pin. this pin sources a constant 12.5a curr ent. by connecting a resistor vs. sgnd it is possible to select between intel and amd integrated dacs and current sense methods. filter with 100pf(max) vs. sgnd. dacs and current sense methods cannot be changed dynamically. see ?dac selection? section and see table 10 for details. 17 outen out put en able pin. forced low, the device stops operat ions with all mosfet off: all the protections are disabled except for section 16.2: preliminary over voltage on page 47 . set free, the device starts-up implement ing soft-start up to the selected vid code. cycle this pin to recover latch from protections; filter with 1nf (typ) vs. sgnd. 18 ssosc/ ref intel mode. s oft s tart osc illator pin. by connecting a resistor r ssosc vs. sgnd, it allows programming the frequency f ss of an internal additional oscillator that drives the reference during soft-start. setting this frequency allows programming the soft-start time t ss proportionally to the r ssosc connected with a gain of 20.1612 [s / k ? ]. the same slope implemented to reach v boot has to be considered also when the reference moves from v boot to the programmed vid code. see ?soft start? section for details. amd mode. ref erence output. filter with 47 ? - 4.7nf vs. sgnd. 19 sgnd all the internal references are referred to this pin. connect to the pcb signal ground. 20 vsen remote buffer output, it manages ovp and uvp protections and pgood (when applicable). see ?output voltage monitor and protections? section and see table 10 for details. 21 droop a current proportional to the total current read is sourced from this pin according to the current reading gain. short to fb to implement droop function or short to sgnd to disable the function.connecting to sgnd through a resistor and filtering with a capacitor, the current info can be used for other purposes. see ?droop function (optional)? section 22 fb error amplifier inverting input. connect with a resistor r fb vs. vsen and with an r f - c f vs. comp. 23 comp error amplifier output. connect with an r f - c f vs. fb. the device cannot be disabled by pulling down this pin. 24 cs4+ channel 4 current sense positive input. ls mosfet sense: connect through a resistor rg to the ls mosfet source. inductor dcr sense: connect through an r-c filter to the phase-side of the channel 4 inductor. see ?layout guidelines? section for proper layout of this connection. table 1. pin functions n pin function
L6714 pin settings 9/70 25 cs4- channel 4 current sense negative input. ls mosfet sense: connect through a resistor rg to the ls mosfet drain. inductor dcr sense: connect through a rg resistor to the output-side of the channel 4 inductor. see ?layout guidelines? section for proper layout of this connection. 26 cs2+ channel 2 current sense positive input. ls mosfet sense: connect through a resistor rg to the ls mosfet source. inductor dcr sense: connect through an r-c filter to the phase-side of the channel 2 inductor. see ?layout guidelines? section for proper layout of this connection. 27 cs2- channel 2 current sense negative input. ls mosfet sense: connect through a resistor rg to the ls mosfet drain. inductor dcr sense: connect through a rg resistor to the output-side of the channel 2 inductor. see ?layout guidelines? section for proper layout of this connection. 28 cs3+ channel 3 current sense positive input. ls mosfet sense: connect through a resistor rg to the ls mosfet source. inductor dcr sense: connect through an r-c filter to the phase-side of the channel 3 inductor. see ?layout guidelines? section for proper layout of this connection. 29 cs3- channel 3 current sense negative input. ls mosfet sense: connect through a resistor rg to the ls mosfet drain. inductor dcr sense: connect through a rg resistor to the output-side of the channel 3 inductor. see ?layout guidelines? section for proper layout of this connection. 30 cs1+ channel 1 current sense positive input. ls mosfet sense: connect through a resistor rg to the ls mosfet source. inductor dcr sense: connect through an r-c filter to the phase-side of the channel 1 inductor. see ?layout guidelines? section for proper layout of this connection. 31 cs1- channel 1 current sense negative input. ls mosfet sense: connect through a resistor rg to the ls mosfet drain. inductor dcr sense: connect through a rg resistor to the output-side of the channel 1 inductor. see ?layout guidelines? section for proper layout of this connection. 32 offset offset programming pin. internally fixed at 1.240v, connecting a r offset resistor vs. sgnd allows setting a current that is mirrored into fb pin in order to program a positive offset according to the selected r fb . short to sgnd to disable the function. see ?offset (optional)? section for details. table 1. pin functions n pin function
pin settings L6714 10/70 33 ovp over voltage programming pin. internally pulled up by 12.5a(typ) to 5v. set free to use built-in protection thresholds as reported into ta b l e 1 0 . connect to sgnd through a r ovp resistor and filter with 100pf (max) to set the ovp threshold to a fixed voltage according to the r ovp resistor. see ?over voltage and programmable ovp? section section for details. 34 vid_sel intel mode. it allows selecting between vr10 (short to sgnd, ta b l e 7 ) or vr11 (floating, ta b l e 6 ) dacs ,internally pulled up by 12.5 a (typ.).. see ?configuring the device? section for details. amd mode. not applicable. needs to be shorted to sgnd. 35 fbr remote buffer non inverting input. connect to the positive side of the load to perform remote sense. see ?layout guidelines? section for proper layout of this connection. 36 fbg remote buffer inverting input. connect to the negative side of the load to perform remote sense. see ?layout guidelines? section for proper layout of this connection. 37 osc/ fault oscillator pin. it allows programming the switching frequency f sw of each channel: the equivalent switching frequency at the load side results in being multiplied by the phase number n. frequency is programmed according to the resistor connected from the pin vs. sgnd or vcc with a gain of 6khz/a (see relevant section for details). leaving the pin floating programs a switch ing frequency of 150khz per phase. the pin is forced high (5v) to signal an ovp fault: to recover from this condition, cycle vcc or the outen pin. see ?oscillator? section for details. 38 vid7/ dvid vid7 - intel mode. see vid5 to vid0 section. dvid - amd mode. dvid output. cmos output pulled high when the contro ller is performing a d-vid transition (with 32 clock cycle delay after the transition has finished). see ?dynamic vid transitions? section section for details. 39 vid6 intel mode. see vid5 to vid0 section. amd mode. not applicable. need to be shorted to sgnd. 40 to 45 vid5 to vid0 intel mode. v oltage id entification pins (also applies to vid6, vid7). internally pulled up by 25a to 5v, connect to sgnd to program a '0' or leave floating to program a '1'. they allow programming output voltage as specified in ta bl e 6 and ta b l e 7 according to vid_sel status. ovp and uvp protection comes as a consequence of the programmed code ( see table 10 ). amd mode. v oltage id entification pins. internally pulled down by 12.5a, leave floating to program a '0' while pull up to more than 1.4v to program a '1'. they allow programming the output voltage as specified in table 9 on page 21 (vid7 doesn?t care). ovp and uvp prot ection comes as a consequence of the programmed code ( see table 10 ). note. vid6 not used, need to be shorted to sgnd. table 1. pin functions n pin function
L6714 pin settings 11/70 46 ss_end/ pgood ssend - intel mode. s oft s tart end signal. open drain output set free after ss has finished and pulled low when triggering any protection. pull up to a voltage lower than 5v (typ), if not used it can be left floating. pgood - amd mode. open drain output set free after ss has finished and pulled low when vsen is lower than the relative threshold. pull up to a voltage lower than 5v (typ), if not used it can be left floating. 47 vr_hot v oltage r egulator hot . over temperature alarm signal. open drain output, set free when tm overcomes the alarm threshold. thermal monitoring output enabled if vcc > uvlo vcc. see ?thermal monitor? section for details and typical connections. 48 vr_fan v oltage r egulator fan . over temperature warning signal. open drain output, set free when tm overcomes the warning threshold. thermal monitoring output enabled if vcc > uvlo vcc. see ?thermal monitor? section for details and typical connections. 49 tm t hermal m onitor input. it senses the regulator temperature through apposite network and drives vr_fan and vr_hot accordingly.short tm pin to sgnd if not used. see ?thermal monitor? section for details and typical connections. 50 sgnd all the internal references are referred to this pin. connect to the pcb signal ground. 51 vccdr4 channel 4 ls driver supply. it must be connected to others vccdrx pins. ls driver supply can range from 5vbus up to 12vbus, filter with 1f mlcc cap vs. pgnd4. 52 lgate4 channel 4 ls driver output. a small series resistor helps in reducing device- dissipated power. 53 pgnd4 channel 4 ls driver return path. connect to power ground plane. 54 pgnd2 channel 2 ls driver return path. connect to power ground plane. 55 lgate2 channel 2 ls driver output. a small series resistor helps in reducing device- dissipated power. 56 vccdr2 channel 2 ls driver supply. it must be connected to others vccdrx pins. ls driver supply can range from 5vbus up to 12vbus, filter with 1f mlcc cap vs. pgnd2. 57 vccdr3 channel 3 ls driver supply. it must be connected to others vccdrx pins. ls driver supply can range from 5vbus up to 12vbus, filter with 1f mlcc cap vs. pgnd3. 58 lgate3 channel 3 ls driver output.a small series resistor helps in reducing device- dissipated power. 59 pgnd3 channel 3 ls driver return path. connect to power ground plane. table 1. pin functions n pin function
pin settings L6714 12/70 60 pgnd1 channel 1 ls driver return path. connect to power ground plane. 61 lgate1 channel 1 ls driver output.a small series resistor helps in reducing device- dissipated power. 62 vccdr1 channel 1 ls driver supply. it must be connected to others vccdrx pins. ls driver supply can range from 5vbus up to 12vbus, filter with 1f mlcc cap vs. pgnd1. 63 phase1 channel 1 hs driver return path. it must be connected to the hs1 mosfet source and provides return path for the hs driver of channel 1. 64 n.c. not internally connected. pa d thermal pa d thermal pad connects the silicon subs trate and makes good thermal contact with the pcb to dissipate the power necessary to drive the external mosfets. connect to the pgnd plane with several vi as to improve thermal conductivity. table 1. pin functions n pin function
L6714 electrical data 13/70 3 electrical data 3.1 maximum rating 3.2 thermal data table 2. absolute maximum ratings symbol parameter value unit v cc , v ccdrx to pgndx 15 v v bootx - v phasex boot voltage 15 v v ugatex - v phasex 15 v v cc - v bootx 7.5 v lgatex, phasex, to pgndx -0.3 to v cc + 0.3 v vid0 to vid7, vid_sel -0.3 to 5 v all other pins to pgndx -0.3 to 7 v v phasex static condition to pgndx, vcc=14v, bootx=7v, phasex=-7.5v -7.5 v positive peak voltage to pgndx; t < 20ns @ 600khz 26 v table 3. thermal data symbol parameter value unit r thja thermal resistance junction to ambient (device soldered on 2s2p pc board) 40 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range 0 to 125 c p tot maximum power dissipation at t a = 25c 2.5 w
electrical characteristics L6714 14/70 4 electrical characteristics v cc = 12v 15%, t j = 0c to 70c, unless otherwise specified table 4. electrical characteristics symbol parameter test condition min. typ. max. unit supply current i cc vcc supply current hgatex and lgatex = open vccdrx = bootx = 12v 17 ma i ccdrx vccdrx supply current lgatex = open; vccdrx = 12v 1ma i bootx bootx supply current hgatex = open; phasex to pgndx; vcc = bootx = 12v 0.75 ma power-on uvlo vcc vcc turn-on vcc rising; vccdrx = 5v 8.9 9.3 v vcc turn-off vcc falling; vccdrx = 5v 7.3 7.7 v uvlo vccdr vccdr turn-on vccdrx rising; vcc = 12v 4.5 4.8 v vccdr turn-off vccdrx falling; vcc = 12v 3.9 4.3 v uvlo ovp pre-ovp turn-on vcc rising; vccdrx = 5v 3.6 3.85 v pre-ovp turn-off vcc falling; vccdrx = 5v 3.05 3.3 v oscillator and inhibit f osc main oscillator accuracy osc = open osc = open; t j = 0c to 125c 135 130 150 165 170 khz t 1 ss delay time intel mode 1 ms t 2 ss time t 2 intel mode; r ssosc = 25k ? 500 s t 3 ss time t 3 intel mode 50 s outen output enable intel mode rising thresholds vo ltage 0.80 0.85 0.90 v hysteresis 100 mv output enable amd mode input low 0.80 v input high 1.40 v pull-up current 12.5 a d max maximum duty cycle osc = open; i droop = 0 a80% osc = open; i droop = 140 a40% ? v osc pwmx ramp amplitude 4 v fault voltage at pin osc ovp active 5 v
L6714 electrical characteristics 15/70 reference and dac k vid output voltage accuracy intel mode vid = 1.000v to vid = 1.600v fbr = vout; fbg = gndout -0.5 - 0.5 % amd mode vid=1.000v to vid = 1.550v fbr = vout; fbg = gndout -0.6 - 0.6 % ref reference accuracy amd mode; respect vid -10 - 10 mv v boot boot voltage intel mode 1.081 v i vid vid pull-up current intel mode; vidx to sgnd 25 a vid pull-down current amd mode; vidx to 5.4v 12.5 a vid il vid thresholds intel mode; input low amd mode; input low 0.3 0.8 v vid ih intel mode; input high amd mode; input high 0.8 1.35 v vid_sel vid_sel threshold (intel mode) input low input high 0.8 0.3 v error amplifier and remote buffer a 0 ea dc gain 80 db sr ea slew rate comp = 10pf to sgnd 20 v/ s rb dc gain 1 v/v cmrr remote buffer common mode rejection ratio 40 db differential curren t sensing and offset i csx+ bias current ls sense inductor sense 25 0 a current sense mismatch rg = 1k ?; i infox = 25 a -3 - 3 % i octh over current threshold i csx- (ocp) - i csx- (0) 30 35 40 a k idroop droop current deviation from nominal value offset = sgnd; rg = 1k ? i droop = 0 to 80 a; -2 - 2 a k ioffset offset current accuracy i offset = 50 a to 250 a-8-8% i offset offset current range 0 250 a v offset offset pin bias i offset = 0 to 250 a1.240v table 4. electrical characteristics symbol parameter test condition min. typ. max. unit i infox i avg ? i avg ------------------------------------------
electrical characteristics L6714 16/70 gate drivers t rise_ugatex hs rise time bootx - phasex = 10v; c ugatex to phasex = 3.3nf 15 30 ns i ugatex hs source current bootx - phasex = 10v 2 a r ugatex hs sink resistance bootx - phasex = 12v 1.5 2 2.5 ? t rise_lgatex ls rise time vccdrx = 10v; c lgatex to pgndx = 5.6nf 30 55 ns i lgatex ls source current vccdrx = 10v 1.8 a r lgatex ls sink resistance vccdrx = 12v 0.7 1.1 1.5 ? protections ovp over voltage protection (vsen rising) intel mode; before v boot 1.300 v intel mode; above vid 100 150 200 mv amd mode 1.700 1.740 1.780 v program- mable ovp i ovp current ovp = sgnd 11.5 12.5 13.5 a comparator offset voltage ovp = 1.8v -50 0 50 mv pre-ovp preliminary over voltage protection uvlo ovp < vcc < uvlo vcc vcc > uvlo vcc & outen = sgnd 1.800 v hysteresis 350 mv uvp under voltage protection vsen falling; below vid -750 mv pgood pgood threshold amd mode; vsen falling; below vid -300 mv v ssend/ pgood ssend / pgood voltage low i = -4ma 0.4 v thermal monitor v tm tm warning (vr_fan) v tm rising 3.2 v tm alarm (vr_hot) v tm rising 3.6 v tm hysteresis 100 mv v vr_hot ; v vr_fan vr_hot voltage low; vr_fan voltage low i = -4ma 0.4 0.4 v v table 4. electrical characteristics symbol parameter test condition min. typ. max. unit
L6714 vid tables 17/70 5 vid tables 5.1 mapping for the intel vr11 mode 5.2 voltage identification (vid) for intel vr11 mode table 5. voltage identification (vid) mapping for intel vr11 mode vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 800mv 400mv 200mv 100mv 50mv 25mv 12.5mv 6.25mv table 6. voltage identification (vid) for intel vr11 mode ( see note ). hex code output voltage (1) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 ) 0 0 off 4 0 1.21250 8 0 0.81250 c 0 0.41250 0 1 off 4 1 1.20625 8 1 0.80625 c 1 0.40625 0 2 1.60000 4 2 1.20000 8 2 0.80000 c 2 0.40000 0 3 1.59375 4 3 1.19375 8 3 0.79375 c 3 0.39375 0 4 1.58750 4 4 1.18750 8 4 0.78750 c 4 0.38750 0 5 1.58125 4 5 1.18125 8 5 0.78125 c 5 0.38125 0 6 1.57500 4 6 1.17500 8 6 0.77500 c 6 0.37500 0 7 1.56875 4 7 1.16875 8 7 0.76875 c 7 0.36875 0 8 1.56250 4 8 1.16250 8 8 0.76250 c 8 0.36250 0 9 1.55625 4 9 1.15625 8 9 0.75625 c 9 0.35625 0 a 1.55000 4 a 1.15000 8 a 0.75000 c a 0.35000 0 b 1.54375 4 b 1.14375 8 b 0.74375 c b 0.34375 0 c 1.53750 4 c 1.13750 8 c 0.73750 c c 0.33750 0 d 1.53125 4 d 1.13125 8 d 0.73125 c d 0.33125 0 e 1.52500 4 e 1.12500 8 e 0.72500 c e 0.32500 0 f 1.51875 4 f 1.11875 8 f 0.71875 c f 0.31875 1 0 1.51250 5 0 1.11250 9 0 0.71250 d 0 0.31250 1 1 1.50625 5 1 1.10625 9 1 0.70625 d 1 0.30625 1 2 1.50000 5 2 1.10000 9 2 0.70000 d 2 0.30000 1 3 1.49375 5 3 1.09375 9 3 0.69375 d 3 0.29375 1 4 1.48750 5 4 1.08750 9 4 0.68750 d 4 0.28750 1 5 1.48125 5 5 1.08125 9 5 0.68125 d 5 0.28125 1 6 1.47500 5 6 1.07500 9 6 0.67500 d 6 0.27500
vid tables L6714 18/70 1 7 1.46875 5 7 1.06875 9 7 0.66875 d 7 0.26875 1 8 1.46250 5 8 1.06250 9 8 0.66250 d 8 0.26250 1 9 1.45625 5 9 1.05625 9 9 0.65625 d 9 0.25625 1 a 1.45000 5 a 1.05000 9 a 0.65000 d a 0.25000 1 b 1.44375 5 b 1.04375 9 b 0.64375 d b 0.24375 1 c 1.43750 5 c 1.03750 9 c 0.63750 d c 0.23750 1 d 1.43125 5 d 1.03125 9 d 0.63125 d d 0.23125 1 e 1.42500 5 e 1.02500 9 e 0.62500 d e 0.22500 1 f 1.41875 5 f 1.01875 9 f 0.61875 d f 0.21875 2 0 1.41250 6 0 1.01250 a 0 0.61250 e 0 0.21250 2 1 1.40625 6 1 1.00625 a 1 0.60625 e 1 0.20625 2 2 1.40000 6 2 1.00000 a 2 0.60000 e 2 0.20000 2 3 1.39375 6 3 0.99375 a 3 0.59375 e 3 0.19375 2 4 1.38750 6 4 0.98750 a 4 0.58750 e 4 0.18750 2 5 1.38125 6 5 0.98125 a 5 0.58125 e 5 0.18125 2 6 1.37500 6 6 0.97500 a 6 0.57500 e 6 0.17500 2 7 1.36875 6 7 0.96875 a 7 0.56875 e 7 0.16875 2 8 1.36250 6 8 0.96250 a 8 0.56250 e 8 0.16250 2 9 1.35625 6 9 0.95625 a 9 0.55625 e 9 0.15625 2 a 1.35000 6 a 0.95000 a a 0.55000 e a 0.15000 2 b 1.34375 6 b 0.94375 a b 0.54375 e b 0.14375 2 c 1.33750 6 c 0.93750 a c 0.53750 e c 0.13750 2 d 1.33125 6 d 0.93125 a d 0.53125 e d 0.13125 2 e 1.32500 6 e 0.92500 a e 0.52500 e e 0.12500 2 f 1.31875 6 f 0.91875 a f 0.51875 e f 0.11875 3 0 1.31250 7 0 0.91250 b 0 0.51250 f 0 0.11250 3 1 1.30625 7 1 0.90625 b 1 0.50625 f 1 0.10625 3 2 1.30000 7 2 0.90000 b 2 0.50000 f 2 0.10000 3 3 1.29375 7 3 0.89375 b 3 0.49375 f 3 0.09375 3 4 1.28750 7 4 0.88750 b 4 0.48750 f 4 0.08750 3 5 1.28125 7 5 0.88125 b 5 0.48125 f 5 0.08125 3 6 1.27500 7 6 0.87500 b 6 0.47500 f 6 0.07500 3 7 1.26875 7 7 0.86875 b 7 0.46875 f 7 0.06875 table 6. voltage identification (vid) for intel vr11 mode ( see note ). hex code output voltage (1) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 )
L6714 vid tables 19/70 5.3 voltage identifications (vid ) for intel vr10 mode + 6.25mv (vid7 does not care) 3 8 1.26250 7 8 0.86250 b 8 0.46250 f 8 0.06250 3 9 1.25625 7 9 0.85625 b 9 0.45625 f 9 0.05625 3 a 1.25000 7 a 0.85000 b a 0.45000 f a 0.05000 3 b 1.24375 7 b 0.84375 b b 0.44375 f b 0.04375 3 c 1.23750 7 c 0.83750 b c 0.43750 f c 0.03750 3 d 1.23125 7 d 0.83125 b d 0.43125 f d 0.03125 3 e 1.22500 7 e 0.82500 b e 0.42500 f e off 3 f 1.21875 7 f 0.81875 b f 0.41875 f f off 1. according to vr11 specs, the device automatically regulates output voltage 19mv lower to avoid any external offset to modify the built-in 0.5% accuracy improving tob performances. output regulated voltage is than what extracted from the t able lowered by 19mv built-in offset. table 6. voltage identification (vid) for intel vr11 mode ( see note ). hex code output voltage (1) hex code output voltage ( 1 ) hex code output voltage ( 1 ) hex code output voltage ( 1 ) table 7. voltage identifications (vid) for intel vr10 mode + 6.25mv ( see note ). vid 4 vid 3 vid 2 vid 1 vid 0 vid 5 vid 6 output voltage (1) vid 4 vid 3 vid 2 vid 1 vid 0 vid 5 vid 6 output voltage (1) 01010111.6 0000 11010111. 20000 01010101.5 9375 11010101. 19375 01011011.5 8750 11011011. 18750 01011001.5 8125 11011001. 18125 01011111.5 7500 11011111. 17500 01011101.5 6875 11011101. 16875 01100011.5 6250 11100011. 16250 01100001.5 5625 11100001. 15625 01100111.5 5000 11100111. 15000 01100101.5 4375 11100101. 14375 01101011.5 3750 11101011. 13750 01101001.5 3125 11101001. 13125 01101111.5 2500 11101111. 12500 01101101.5 1875 11101101. 11875 01110011.5 1250 11110011. 11250 01110001.5 0625 11110001. 10625
vid tables L6714 20/70 01110111.5 0000 11110111. 10000 01110101.4 9375 11110101. 09375 01111011.4 8750 1111101 off 01111001.4 8125 1111100 off 01111111.4 7500 1111111 off 01111101.4 6875 1111110 off 10000011.4 6250 00000011. 08750 10000001.4 5625 00000001. 08125 10000111.4 5000 00000111. 07500 10000101.4 4375 00000101. 06875 10001011.4 3750 00001011. 06250 10001001.4 3125 00001001. 05625 10001111.4 2500 00001111. 05000 10001101.4 1875 00001101. 04375 10010011.4 1250 00010011. 03750 10010001.4 0625 00010001. 03125 10010111.4 0000 00010111. 02500 10010101.3 9375 00010101. 01875 10011011.3 8750 00011011. 01250 10011001.3 8125 00011001. 00625 10011111.3 7500 00011111. 00000 10011101.3 6875 00011100. 99375 10100011.3 6250 00100010. 98750 10100001.3 5625 00100000. 98125 10100111.3 5000 00100110. 97500 10100101.3 4375 00100100. 96875 10101011.3 3750 00101010. 96250 10101001.3 3125 00101000. 95625 10101111.3 2500 00101110. 95000 10101101.3 1875 00101100. 94375 10110011.3 1250 00110010. 93750 10110001.3 0625 00110000. 93125 10110111.3 0000 00110110. 92500 table 7. voltage identifications (vid) for intel vr10 mode + 6.25mv ( see note ). vid 4 vid 3 vid 2 vid 1 vid 0 vid 5 vid 6 output voltage (1) vid 4 vid 3 vid 2 vid 1 vid 0 vid 5 vid 6 output voltage (1)
L6714 vid tables 21/70 5.4 mapping for the amd 6bit mode 5.5 voltage identifications (v id) codes for amd 6bit mode 10110101.2 9375 00110100. 91875 10111011.2 8750 00111010. 91250 10111001.2 8125 00111000. 90625 10111111.2 7500 00111110. 90000 10111101.2 6875 00111100. 89375 11000011.2 6250 01000010. 88750 11000001.2 5625 01000000. 88125 11000111.2 5000 01000110. 87500 11000101.2 4375 01000100. 86875 11001011.2 3750 01001010. 86250 11001001.2 3125 01001000. 85625 11001111.2 2500 01001110. 85000 11001101.2 1875 01001100. 84375 11010011.2 1250 01010010. 83750 11010001.2 0625 01010000. 83125 1. according to vr10.x specs, the device automaticall y regulates output voltage 19mv lower to avoid any external offset to modify the built-in 0.5% accuracy improving tob performances. output regulated voltage is than what extracted from the table lower ed by 19mvbuilt-in offset. vid7 doesn?t care. table 7. voltage identifications (vid) for intel vr10 mode + 6.25mv ( see note ). vid 4 vid 3 vid 2 vid 1 vid 0 vid 5 vid 6 output voltage (1) vid 4 vid 3 vid 2 vid 1 vid 0 vid 5 vid 6 output voltage (1) table 8. voltage identifications (vid) mapping for amd 6bit mode vid4 vid3 vid2 vid1 vid0 400mv 200mv 100mv 50mv 25mv table 9. voltage identifications (vid) codes for amd 6bit mode ( see note ). vid 5 vid 4 vid 3 vid 2 vid 1 vid 0 output voltag e (1) vid 5 vid 4 vid 3 vid 2 vid 1 vid 0 output voltage ( 1 ) 0 0 0 0 0 0 1.5500 1 0 0 0 0 0 0.7625 0 0 0 0 0 1 1.5250 1 0 0 0 0 1 0.7500 0 0 0 0 1 0 1.5000 1 0 0 0 1 0 0.7375 0 0 0 0 1 1 1.4750 1 0 0 0 1 1 0.7250
vid tables L6714 22/70 0 0 0 1 0 0 1.4500 1 0 0 1 0 0 0.7125 0 0 0 1 0 1 1.4250 1 0 0 1 0 1 0.7000 0 0 0 1 1 0 1.4000 1 0 0 1 1 0 0.6875 0 0 0 1 1 1 1.3750 1 0 0 1 1 1 0.6750 0 0 1 0 0 0 1.3500 1 0 1 0 0 0 0.6625 0 0 1 0 0 1 1.3250 1 0 1 0 0 1 0.6500 0 0 1 0 1 0 1.3000 1 0 1 0 1 0 0.6375 0 0 1 0 1 1 1.2750 1 0 1 0 1 1 0.6250 0 0 1 1 0 0 1.2500 1 0 1 1 0 0 0.6125 0 0 1 1 0 1 1.2250 1 0 1 1 0 1 0.6000 0 0 1 1 1 0 1.2000 1 0 1 1 1 0 0.5875 0 0 1 1 1 1 1.1750 1 0 1 1 1 1 0.5750 0 1 0 0 0 0 1.1500 1 1 0 0 0 0 0.5625 0 1 0 0 0 1 1.1250 1 1 0 0 0 1 0.5500 0 1 0 0 1 0 1.1000 1 1 0 0 1 0 0.5375 0 1 0 0 1 1 1.0750 1 1 0 0 1 1 0.5250 0 1 0 1 0 0 1.0500 1 1 0 1 0 0 0.5125 0 1 0 1 0 1 1.0250 1 1 0 1 0 1 0.5000 0 1 0 1 1 0 1.0000 1 1 0 1 1 0 0.4875 0 1 0 1 1 1 0.9750 1 1 0 1 1 1 0.4750 0 1 1 0 0 0 0.9500 1 1 1 0 0 0 0.4625 0 1 1 0 0 1 0.9250 1 1 1 0 0 1 0.4500 0 1 1 0 1 0 0.9000 1 1 1 0 1 0 0.4375 0 1 1 0 1 1 0.8750 1 1 1 0 1 1 0.4250 0 1 1 1 0 0 0.8500 1 1 1 1 0 0 0.4125 0 1 1 1 0 1 0.8250 1 1 1 1 0 1 0.4000 0 1 1 1 1 0 0.8000 1 1 1 1 1 0 0.3875 0 1 1 1 1 1 0.7750 1 1 1 1 1 1 0.3750 1. vid6 not applicable, need to be left unconnected. table 9. voltage identifications (vid) codes for amd 6bit mode ( see note ). vid 5 vid 4 vid 3 vid 2 vid 1 vid 0 output voltag e (1) vid 5 vid 4 vid 3 vid 2 vid 1 vid 0 output voltage ( 1 )
L6714 reference schematic 23/70 6 reference schematic figure 3. reference schematic - intel vr10.x, vr11 inductor sense fbr fbg l1 2 1 63,64 boot1 ugate1 phase1 lgate1 61 pgnd1 60 cs1- 31 cs1+ 30 rg hs1 ls1 l2 10 9 7,8 boot2 ugate2 phase2 lgate2 55 pgnd2 54 cs2- 27 cs2+ 26 hs2 ls2 l3 6 5 3,4 boot3 ugate3 phase3 lgate3 58 pgnd3 59 cs3- 29 cs3+ 28 rg r hs3 ls3 ss_end / pgood 46 c out vcc_core load 36 35 vsen 20 fb 22 r fb comp 23 r f c f vid4 41 vid3 42 vid2 43 vid1 44 vid0 45 vid_sel 34 vid5 40 ovp 33 offset 32 osc/fault 37 vcc 15 sgnd 19,50 vccdr3 57 vccdr2 56 vccdr1 62 l in v in gnd in c in L6714 L6714 ref. sch. (inductor - intel mode) c r c rg r c 39 38 vid6 vid7 / dvid outen 17 outen droop 21 ssosc / ref 18 vid bus from cpu dac / cs_sel 16 tm 49 vr_fan 48 vr_hot 47 +5v ntc l4 14 13 11,12 boot4 ugate4 phase4 lgate4 52 pgnd4 53 cs4- 25 cs4+ 24 rg r hs4 ls4 c ss_end vccdr4 51 to boot1 to boot2 to boot3 to boot4 v in v in v in v in vid_sel
reference schematic L6714 24/70 figure 4. reference schematic - intel vr10.x, vr11 ls mosfet sense fbr fbg l1 2 1 63,64 boot1 ugate1 phase1 lgate1 61 pgnd1 60 cs1- 31 cs1+ 30 rg l2 10 9 7,8 boot2 ugate2 phase2 lgate2 55 pgnd2 54 cs2- 27 cs2+ 26 l3 6 5 3,4 boot3 ugate3 phase3 lgate3 58 pgnd3 59 cs3- 29 cs3+ 28 rg ssend / pgood 46 c out vcc_core load 36 35 vsen 20 fb 22 r fb comp 23 r f c f vid4 41 vid3 42 vid2 43 vid1 44 vid0 45 vid_sel 34 vid5 40 ovp 33 offset 32 osc/fault 37 vcc 15 sgnd 19,50 vccdr3 57 vccdr2 56 vccdr1 62 l in v in gnd in L6714 L6714 ref. sch. (mosfet - intel mode) rg 39 38 vid6 vid7 / d-vid outen 17 outen droop 21 ssosc / ref 18 dac / cs_sel 15 tm 49 vr_fan 48 vr_hot 47 +5v ntc l4 14 13 11,12 boot4 ugate4 phase4 lgate4 52 pgnd4 53 cs4- 25 cs4+ 24 rg pgood vccdr4 51 rg rg rg rg c in to boot1 to boot2 to boot3 to boot4 hs1 ls1 v in hs2 ls2 v in hs3 ls3 v in hs4 ls4 v in vid_sel vid bus from cpu 170k
L6714 reference schematic 25/70 figure 5. reference schematic - amd 6bit inductor sense fbr fbg l1 2 1 63,64 boot1 ugate1 phase1 lgate1 61 pgnd1 60 cs1- 31 cs1+ 30 rg hs1 ls1 l2 10 9 7,8 boot2 ugate2 phase2 lgate2 55 pgnd2 54 cs2- 27 cs2+ 26 hs2 ls2 l3 6 5 3,4 boot3 ugate3 phase3 lgate3 58 pgnd3 59 cs3- 29 cs3+ 28 rg r hs3 ls3 ss_end / pgood 46 c out vcc_core load 36 35 vsen 20 fb 22 r fb comp 23 r f c f vid4 41 vid3 42 vid2 43 vid1 44 vid0 45 vid_sel 34 vid5 40 ovp 33 offset 32 osc/fault 37 vcc 15 sgnd 19,50 vccdr3 57 vccdr2 56 vccdr1 62 l in v in gnd in c in L6714 L6714 ref. sch. (inductor - amd 6bit mode) c r c rg r c 39 38 vid6 vid7 / dvid outen 17 outen droop 21 ssosc / ref 18 dac / cs_sel 16 tm 49 vr_fan 48 vr_hot 47 +5v ntc l4 14 13 11,12 boot4 ugate4 phase4 lgate4 52 pgnd4 53 cs4- 25 cs4+ 24 rg r hs4 ls4 c ss_end vccdr4 51 to boot1 to boot2 to boot3 to boot4 v in v in v in v in vid bus from cpu 270k
reference schematic L6714 26/70 figure 6. reference schematic - amd 6bit ls mosfet sense fbr fbg l1 2 1 63,64 boot1 ugate1 phase1 lgate1 61 pgnd1 60 cs1- 31 cs1+ 30 rg l2 10 9 7,8 boot2 ugate2 phase2 lgate2 55 pgnd2 54 cs2- 27 cs2+ 26 l3 6 5 3,4 boot3 ugate3 phase3 lgate3 58 pgnd3 59 cs3- 29 cs3+ 28 rg ssend / pgood 46 c out vcc_core load 36 35 vsen 20 fb 22 r fb comp 23 r f c f vid4 41 vid3 42 vid2 43 vid1 44 vid0 45 vid_sel 34 vid5 40 ovp 33 offset 32 osc/fault 37 vcc 15 sgnd 19,50 vccdr3 57 vccdr2 56 vccdr1 62 l in v in gnd in L6714 L6714 ref. sch. (mosfet - amd 6bit mode) rg 39 38 vid6 vid7 / d-vid outen 17 outen droop 21 ssosc / ref 18 vid bus from cpu dac / cs_sel 15 tm 49 vr_fan 48 vr_hot 47 +5v ntc l4 14 13 11,12 boot4 ugate4 phase4 lgate4 52 pgnd4 53 cs4- 25 cs4+ 24 rg pgood vccdr4 51 rg rg rg rg c in to boot1 to boot2 to boot3 to boot4 hs1 ls1 v in hs2 ls2 v in hs3 ls3 v in hs4 ls4 v in
L6714 device description 27/70 7 device description L6714 is four-phase pwm controller with embedded high current drivers that provides complete control logic and protections for a high performance step-down dc-dc voltage regulator optimized for advanced microprocessor power supply. multi phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current vrm modules. it allows distributing equally load and power between the phases using smaller, cheaper and most common external power mosfet and inductors. moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. phase interleaving causes in fact input rms current and output ripple voltage reduction and show an effective output switching frequency increase: the 150khz free-running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases. L6714 permits easy and flexible system design by allowing current reading across either inductor or low side mosfet in fully differential mode simply selecting the desired way through apposite pin. in both cases, also a sense resistor in series to the related element can be considered to improve reading precision. the current information read corrects the pwm output in order to equalize the average current carried by each phase limiting the error at 3% over static and dynamic conditions unless considering the sensing element spread. the controller includes multiple dacs, sele ctable through an apposite pin, allowing compatibility with both intel vr10,vr11 and amd 6bit proce ssors specifications, also performing d-vid transitions accordingly. low-side-less start-up allows soft start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side. L6714 provides programmable over-voltage protection to protect the load from dangerous over stress. it can be externally set to a fixed voltage through an apposite resistor, or it can be set internally, latching immediately by turning on the lower driver and driving high the fault pin. furthermore, preliminary ovp protection also allows the device to protect load from dangerous ovp when vcc is not above the uvlo threshold. the over-current protection provided, with an oc threshold for each phase, causes the device to enter in constant current mode until the latched uvp. L6714 provides system thermal monitoring: th rough an apposite pin the device senses the temperature of the hottest component in the application driving the warning and the alarm signal as a consequence. a compact 10x10mm body tqfp64 package with exposed thermal pad allows dissipating the power to drive the external mosfet through the system board.
configuring the device L6714 28/70 8 configuring the device multiple dacs and different current reading methodologies need to be configured before the system starts-up by programming the apposite pin dac/cs_sel. the configuration of this pin identifies two main working areas ( see table 10 ) distinguishing between compliancy with intel vr10,vr11 or amd 6bit specifications. according to the main specification considered, further customs can be done: main differences are regarding the dac table, soft-start implementation, protection management and dynamic vid transitions. of course, the current reading method can be still selected through dac / cs_sel pin. see table 11 and see table 12 for further details about the device configuration. 8.1 dac selection L6714 embeds a selectable dac (through dac/cs_sel, see table 10 ) that allows to regulate the output voltage with a tolerance of 0.5% (0.6% for amd dac) recovering from offsets and manufacturing variations. in case of selecting intel mode, the device automatically introduces a -19mv (both vrd10.x and vr11) offset to the regulated voltage in order to avoid any external offset circuitry to worsen the guaranteed accuracy and, as a consequence, the calculated system tob. note: filter dac/cs_sel pin with 100pf(max) vs. sgnd. output voltage is programmed through the vid pins: they are inputs of an internal dac that is realized by means of a series of resistors providing a partition of the internal voltage reference. the vid code drives a multiplexer that selects a voltage on a precise point of the divider. the dac output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, v ref ). table 10. dac / cs_sel settings ( see note ). dac / cs_sel resistance vs. sgnd dac current sense method ovp uvp 0 (short) intel inductor dcr vid + 150mv (typ) or programmable -750mv (typ) 170k ? mosfet r dson 270k ? amd inductor dcr 1.800v (typ) or programmable -750mv (typ) open mosfet r dson
L6714 configuring the device 29/70 note: vid pull-ups / pull-downs, vid voltage thresholds and outen thresholds changes according to the selected dac: see table 4 for details. note: vid pull-ups / pull-downs, vid voltage thresholds and outen thresholds changes according to the selected dac: see table 4 for details. table 11. intel mode configuration ( see note ). pin function typical connection dac / cs_sel it allows selecting the intel mode and, furthermore, between inductor or ls mosfet current reading. static info, no dynamic changes allowed. sgnd: inductor sense; 170k ? to sgnd: ls mosfet sense. filter with 100pf(max). ssosc / ref it allows programming the soft-start time t ss . see ?soft start? section for details. resistor r ssosc vs. sgnd. vid_sel it allows selecting between vr11 dac or vr10.x + 6.25mv extended dac. static info, no dynamic changes allowed. open: vr11 ( ta b l e 6 ). short to sgnd: vr10.x ( ta b l e 7 ). vid7 to vid0 they allow programming the output voltage according to ta b l e 6 and ta bl e 7 . dynamic transitions managed, see ?dynamic vid transitions? section for details. open: logic ?1? (25 a pull-up) short to sgnd: ?0? ssend / pgood soft start end signal set free after soft-start has finished. it only indicates soft-start has finished. pull-up to anything lower than 5v. table 12. amd mode configuration ( see note ). pin function typical connection dac / cs_sel it allows selecting the amd mode and, furthermore, between indu ctor or ls mosfet current reading. static info, no dynamic changes allowed. 270k ? to sgnd: inductor sense; open: ls mosfet sense; filter with 100pf(max). ssosc / ref the reference used for the regulation is available on this pin. filter with 47 ? - 4.7nf vs. sgnd. vid_sel not applicable need to be shorted to sgnd. vid7 / dvid pulled high when performing a d-vid transition. the pin is kept high with a 32 clock cycles delay. not applicable vid6 not applicable needs to be shorted to sgnd vid5 to vid0 they allow programming the output voltage according to ta bl e 9 . dynamic transitions managed, see ?dynamic vid transitions? section for details. open: ?0? (12.5 a pull-down) pull-up to v > 1.4v: ?1? ssend / pgood power good signal set free after soft-start has finished whenever the output voltage is within limits. pull-up to anything lower than 5v.
power dissipation L6714 30/70 9 power dissipation L6714 embeds high current mosfet drivers for both high side and low side mosfet: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. in addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between junction and ambient consequent to the layout is also important: thermal pad need to be soldered to the pcb ground plane through seve ral vias in order to facilitate the heat dissipation. two main terms contribute to the device power dissipation: bias power and drivers' power. the first one (p dc ) depends on the static consumption of the device through the supply pins and is simply quantifiable as follows (assuming to supply hs and ls drivers with the same vcc of the device): where n is the number of phases. drivers' power is the power needed by the driver to continuously switch on and off the external mosfet; it is a function of the switching frequency and total gate charge of the selected mosfet. it can be quantified considering that the total power p sw dissipated to switch the mosfet (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet re sistance and intrinsic driver resistance. this last term is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfet results: external gate resistors help the device to dissipate the switching power since the same power p sw will be shared between the internal driv er impedance and the external resistor resulting in a general cooling of the device. when driving multiple mosfet in parallel, it is suggested to use one gate resistor for each mosfet. p dc v cc i cc ni ccdrx ? ni bootx ? ++ () ? = p sw nf sw q ghs v boot ? q gls v ccdrx ? + () ?? =
L6714 power dissipation 31/70 figure 7. L6714 dissipated power (quiescent + switching). L6714; rgate=0; rmosfet=0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 50 100 150 200 250 300 350 400 450 500 550 switching frequency [khz] per phase controller dissipated power [mw] hs=1xstd38nh02l; ls=1xstd90nh02l hs=2xstd38nh02l; ls=2xstd90nh02l hs=1xstd55nh22l; ls=1xstd95nh02l hs=2xstd55nh22l; ls=2xstd95nh02l hs=3xstd55nh22l; ls=3xstd95nh02l L6714; rhs=2.2; rls=3.3; rmosfet=1 0 1000 2000 3000 4000 5000 6000 7000 50 100 150 200 250 300 350 400 450 500 550 switching frequency per phase [khz] controller dissipated power [mw] hs=1xstd38nh02l; ls=1xstd90nh02l hs=2xstd38nh02l; ls=2xstd90nh02l hs=1xstd55nh2ll; ls=1xstd95nh02l hs=2xstd55nh2ll; ls=2xstd95nh02l hs=3xstd55nh2ll; ls=3xstd95nh02l
current reading and current sharing loop L6714 32/70 10 current reading and current sharing loop L6714 embeds a flexible, fully-dif ferential current sense circuitry that is able to read across both low side or inductor parasi tic resistance or across a sense resistor placed in series to that element. the fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy. the kind of sense element can be simply chosen through the dac/cs_sel pin according to see ta bl e 1 0 . current sharing contro l loop reported in figure 8 : it considers a current i infox proportional to the current delivered by each phase and the average current . the error between the read current i infox and the reference i avg is then converted into a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by the voltage error amplifier in order to equalize the current carried by each phase. details about connections are shown in figure 9 . figure 8. current sharing loop. i avg i infox n ( ) ? = i info1 pwm1 out from ea i info2 i avg pwm2 out i info3 pwm3 out avg pwm4 out i info4
L6714 current reading and current sharing loop 33/70 10.1 low side current reading when reading current across ls, the current flowing trough each phase is read using the voltage drop across the low side mosfet r dson or across a sense resistor in its series and it is internally converted into a current. the trans-conductance ratio is issued by the external resistor rg placed outside the chip between csx- and csx+ pins toward the reading points. the current sense circuit tracks the current information for a time t track centered in the middle of the ls conduction time and holds the tracked information during the rest of the period. L6714 sources a constant 25 a bias current from the csx+ pin: the current reading circuitry uses this pin as a reference and the reaction keeps the csx- pin to this voltage during the reading time (an internal clamp keeps csx+ and csx- at the same voltage sinking from the csx- pin the necessary current during the hold time; this is needed to avoid absolute maximum rating overcome on csx- pin). the current that flows from the csx- pin is then given by ( see figure 9 ): where r dson is the on resistance of the low side mosfet and rg is the trans-conductance resistor used between csx- and csx+ pins toward the reading points; i phasex is the current carried by the relative phase and i infox is the current information signal reproduced internally. 25 a offset allows negative current reading, enabling the device to check for dangerous returning current between the phases assuring the complete current equalization. 10.2 inductor current reading when reading current across the inductor dcr, the current flowing trough each phase is read using the voltage drop across the output inductor or across a sense resistor in its series and internally converted into a current. the trans-conductance ratio is issued by the external resistor rg placed outside the chip between csx- pin toward the reading points. the current sense circuit always tracks the current information, no bias current is sourced from the csx+ pin: this pin is used as a refe rence keeping the csx- pin to this voltage. to correctly reproduce the inductor current an r-c filtering network must be introduced in parallel to the sensing element. the current that flows from the csx- pin is then given by the following equation ( see figure 9 ): where i phasex is the current carried by the relative phase. i csx- 25 a r dson rg ----------------- i phasex ? + 25 ai infox + == i csx- r l rg ------- - 1s l r l ? ? + 1s r c ?? + ------------------------------------- i ? phasex ? =
current reading and current sharing loop L6714 34/70 figure 9. current reading connections. considering now to match the time constant between the inductor and the r-c filter applied (time constant mismatches caus e the introduction of poles into the current reading network causing instability. in addition, it is also important for the load transient response and to let the system show resistive equivalent output impedance), it results: where i infox is the current information reproduced internally. csx- csx+ lgatex i phasex lx csx+ csx- phasex r lx r c rg rg rg i phasex ls mosfet r dson current sense inductor dcr current sense i csx- 25 a i csx- =i infox no bias l r l ------ - rc i csx- r l rg ------- - i phasex ? = ? ? i infox i infox r l rg ------- - i phasex ? = ? ==
L6714 remote voltage sense 35/70 11 remote voltage sense the device embeds a remote sense buffer to sense remotely the regulated voltage without any additional external components. in this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard or connector losses. it senses the output voltage remotely through the pins fbr and fbg (fbr is for the regulated voltage sense while fbg is for the gro und sense) and reports this voltage in ternally at vsen pin with unity gain eliminating the errors. keeping the fbr and fbg traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. if remote sense is not required, it is enough connecting the resistor r fb directly to the regulated voltage: vsen beco mes not connected and still se nses the output voltage through the remote buffer. in this case the fbg and fbr pins must be connected anyway to the regulated voltage ( see figure 10 ). warning: the remote buffer is included in the trimming chain in order to achieve 0.5% accuracy (0.6% for the amd dac) on the output voltage when the rb is used: eliminating it from the control loop causes the regulation error to be increased by the rb offset worsening the device performances. figure 10. remote buffer connections v ref fb comp vsen 64k fbr fbg 64k 64k 64k r f c f r fb to vcore (remote sense) fb comp vsen 64k fbr fbg 64k 64k 64k r f c f r fb to vcore remote buffer used (up to 0.5% accuracy) remote buffer not used (precision worsened) v ref
voltage positioning L6714 36/70 12 voltage positioning output voltage positioning is performed by selecting the reference dac and by programming the droop function and offset to the reference ( see figure 11 ). the currents sourced from droop and fb pins cause the output voltage to vary according to the external r fb resistor. in addition, the embedded remote buffer allows to precisely programming the output voltage offsets and variations by recovering the voltage drops across distribution lines. the output voltage is then driv en by the following relationship: where droop function can be disabled as well as the offset: connecting droop pin and fb pin together implements the load regulation dependence while, if this effect is not desired, by shorting droop pin to sgnd it is possible for the device to operate as a classic voltage mode buck converter. the droop pin can also be connected to sgnd through a resistor obtaining a voltage proportional to the delivered current usable for monitoring purposes. offset can be disabled by shorting the relative pin to sgnd. v out v ref r fb i droop i offset ? () ? ? = v ref vid 19mv ? vr10 - vr11 vid amd 6bit ? ? ? =
L6714 voltage positioning 37/70 12.1 droop function (optional) this method "recovers" part of the drop due to the output capacitor esr in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. as shown in figure 11 , the esr drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. moreover, more and more high- performance cpus require precise load-line regulation to perform in the proper way. droop function is not then required only to optimize the output filter, but also beacomes a requirement of the load. connecting droop pin and fb pin together, the device forces a current i droop , proportional to the read current, into the feedback resistor r fb implementing the load regulation dependence. since i droop depends on the current information about the three phases, the output characteristic vs. load current is then given by: where r sense is the chosen sensing element re sistance (inductor dcr or ls r dson ) and i out is the output current of the system. the whole power supply can be then represented by a "real" voltage generator with an equivalent output resistance r droop and a voltage value of v ref . r fb resistor can be also designed according to the r droop specifications as follow: droop function is optional, in case it is not desired, the droop pin can be disconnected from the fb and an information about the total delivered current becomes available for debugging, and/or current monitoring. when not used, the pin can be shorted to sgnd. figure 11. voltage positioning (left) and droop function (right) v out v ref r fb i droop ? ? v ref r fb r sense rg --------------------- i out ?? ? v ref r droop i out ? ? == = r fb r droop rg r sense --------------------- ? = i droop v ref fb comp i offset vsen 64k fbr fbg 64k 64k 64k r f c f r fb to vcore (remote sense) esr drop v max v min v nom response without droop response with droop droop
voltage positioning L6714 38/70 12.2 offset (optional) the offset pin allows programming a positive offset (v os ) for the output voltage by connecting a resistor r offset vs. sgnd; this offset has to be considered in addition to the one already introduced during the production stage for the intel vr10,vr11 mode. the offset pin is internally fixed at 1.240v ( see table 4 ) a current is programmed by connecting the resistor r offset between the pin and sgnd: this current is mirrored and then properly sunk from the fb pin as shown in figure 12 . output voltage is then programmed as follow: offset resistor can be designed by considering the following relationship (r fb is fixed by the droop effect): offset automatically given by the dac selection differs from the offset implemented through the offset pin: the built-in feature is trimmed in production and assures 0.5% error (0.6% for the amd dac) over load and line variations. figure 12. voltage positioning with offset v out v ref r fb i droop i offset ? () ? ? = r offset 1.240v v os ------------------ - r fb ? = 1.240v r offset offset v ref fb comp vsen 64k fbr fbg 64k 64k 64k r f c f r fb to vcore (remote sense) i droop i offset i offset droop
L6714 dynamic vid transitions 39/70 13 dynamic vid transitions the device is able to manage dynamic vid code changes that allow output voltage modification during normal device operation. ovp and uvp signals (and pgood in case of amd mode) are masked during every vid transition and they are re-activated after the transition finishes with a 32 clock cycles delay to prevent from false triggering due to the transition. when changing dynamically the regulated voltage (d -vid), the system needs to charge or discharge the output capacitor accordingly. this means that an extra-current i d-vid needs to be delivered, especially when increasing the output regulated voltage and it must be considered when setting the over current threshold. this current can be estimated using the following relationships: where dv out is the selected dac lsb (6.25mv for vr11 and vr10 extended dac or 25mv for amd dac) and t vid is the time interval between each lsb transition (externally driven). overcoming the oc threshold during the dynamic vid causes the device to enter the constant current limitation slowing down the output voltage dv/dt also causing the failure in the d-vid test. L6714 checks for vid code modifications ( see figure 13 ) on the rising edge of an internal additional dvid-clock and waits for a confirmation on the following falling edge. once the new code is stable, on the next rising edge, the reference starts stepping up or down in lsb increments every vid-clock cycle until the new vid code is reached. during the transition, vid code changes are ignored; the device re-starts monitoring vid after the transition has finished on the next rising edge available. vid-clock frequency (f dvid ) depends on the operative mode selected: for intel mode it is in the range of 1mhz to assure compatibility with the specifications while, for amd mode, th is frequency is lowered to about 250khz. when L6714 performs a d-vid transition in am d mode, dvid pin is pulled high as long as the device is performing the transition (also including the additional 32clocks delay) warning: if the new vid code is more than 1 lsb different from the previous, the device will execute the transition stepping the reference with the dvid-clock frequency f dvid until the new code has reached: for this reason it is recommended to carefully control the vid change rate in order to carefully control the slope of the output voltage variation especially in intel mode. i dvid ? c out dv out dt vid ----------------- - ? =
dynamic vid transitions L6714 40/70 figure 13. dynamic vid transitions t dvid x 4 step vid transition t t t vid sampled vid sampled vid sampled ref moved (1) ref moved (2) ref moved (3) ref moved (4) vid stable vid [0,7] int. reference v out t sw vid sampled vid sampled ref moved (1) ref moved (1) ref moved (1) vid sampled vid sampled 4 x 1 step vid transition t vid vid sampled vid sampled vid sampled vid sampled vid sampled vid stable vid stable vid stable ref moved (1) vid sampled vid sampled vid stable vid sampled vid sampled vid sampled t vid clock vout slope controlled by internal dvid-clock oscillator vout slope controlled by external driving circuit (t vid )
L6714 enable and disable 41/70 14 enable and disable L6714 has three different supplies: vcc pin to supply the internal control logic, vccdrx to supply the low side drivers and bootx to supply the high side drivers. if the voltage at pins vcc and vccdrx are not above the turn on thresholds specified in the electrical characteristics , the device is shut down: all drivers keep the mosfet off to show high impedance to the load. once the device is correctly supplied, proper operation is assured and the device can be driven by the outen pin to control the power sequencing. setting the pin free, the device implements a soft start up to the programmed voltage. shorting the pin to sgnd, it resets the devi ce (ss_end/pgood is shorted to sgnd in this condition) from any latched condition and also disables the device keeping all the mosfet turned off to show high impedance to the load.
soft start L6714 42/70 15 soft start L6714 implements a soft-start to smoothly charge the output filter avoiding high in-rush currents to be required to the input power supply. the device increases the reference from zero up to the programmed value in different ways according to the selected operative mode and the output voltage increases accordingly with closed loop regulation. the device implements soft-start only when all the power supplies are above their own turn- on thresholds and the outen pin is set free. at the end of the digital soft-start, ss_end/pgood signal is set free. protections are active during this phase; under voltage is e nabled when the reference voltage reaches 0.6v while over voltage is always enabled with a threshold dependent on the selected operative mode or with the fixed threshold programmed by r ovp ( see ?over voltage and programmable ovp? section ). figure 14. soft start outen ss_end intel mode v out t t t t 1 t 2 t 3 t 4 t ss outen pgood amd 6bit mode v out t t t t ss ovp
L6714 soft start 43/70 15.1 intel mode once L6714 receives all the correct supplies and enables, and intel mode has been selected, it initiates the soft-start phase with a t 1 = 1ms (min) delay. after that, the reference ramps up to v boot = 1.081v (1.100v - 19mv) in t 2 according to the ssosc settings and waits for t 3 = 75 sec (typ) during which the device reads the vid lines. output voltage will then ramps up to the programmed value in t 4 with the same slope as before ( see figure 14 ). ssosc defines the frequency of an internal additional soft-st art-oscillator used to step the reference from zero up to th e programmed value; this oscilla tor is independent from the main oscillator whose fr equency is programmed through the osc pin. ssosc sets then the output voltage dv/dt during soft-start according to the resistor r ssosc connected vs. sgnd. in particular, it allows to precisely programming the start-up time up to v boot (t 2 ) since it is a fixed voltage independent by the programmed vid. total soft-start time dependence on the programmed vid results ( see figure 15 ): where t ss is the time spent to reach the programmed voltage v ss and r ssosc the resistor connected between ssosc and sgnd in k ? . protections are active during soft-start, uvp is enabled after the reference reaches 0.6v while ovp is always active with a fixed 1.24v threshold before v boot and with the threshold coming from the vid (or the programmed v ovp ) after v boot (see red-dashed line in figure 14 ). note: if during t 3 the programmed vid selects an output voltage lower than v boot , the output voltage will ramp to the progra mmed voltage starting from v boot . r ssosc k ? [] t 2 s [] 4.9783 10 2 ? ?? = t ss s [] 1075 s [] r ssosc k ? [] 5.3816 10 2 ? ? ------------------------------------- v ss ? if v ss v boot > () r ssosc k ? [] 5.3816 10 2 ? ? ------------------------------------- v boot v boot v ss ? () + [] ? if v ss v boot < () ? ? ? ? ? ? ? + =
soft start L6714 44/70 figure 15. soft-start time for intel mode. 15.2 amd mode once L6714 receives all the correct supplies and enables, and amd mode has been selected, it initiates the soft-start by stepping the reference from zero up to the programmed vid code ( see figure 14 ); the clock now used to step the reference is the same as the main oscillator programmed by the osc pin, ssosc pi n is not applicable in this case. the soft- start time results then ( see figure 16 ): where t ss is the time spent to reach v ss and f sw is the main switching frequency programmed by osc pin. protections are active during soft-start, uvp is enabled after the reference reaches 0.6v while ovp is always active with the fixed 1.800v threshold (or the programmed v ovp ). 0 1 2 3 4 5 6 7 8 1 10 100 1000 rssosc [k ohms ] vs. sgnd soft start time tss [ms] time to vboot time to 1.6000v dv out dt ------------------ 3.125 f sw kkhz [] ? = t ss v ss 3.125 f sw khz [] ? ------------------------------------------------- - = ?
L6714 soft start 45/70 figure 16. soft-start time for amd mode 0 0.5 1 1.5 2 2.5 3 3.5 4 0 200 400 600 800 1000 rosc [kohms] to sgnd softstart time tss [msec] 150 200 250 300 350 400 450 500 550 switching freqency [khz] time to 1.6000v time to 1.1000v switching frequency per phase 0 0.5 1 1.5 2 2.5 3 3.5 4 0 200 400 600 800 1000 rosc [kohms] to sgnd softstart time tss [msec] 150 200 250 300 350 400 450 500 550 switching freqency [khz] time to 1.6000v time to 1.1000v switching frequency per phase
soft start L6714 46/70 15.3 low-side-less startup in order to avoid any kind of negative undershoot on the load side during start-up, L6714 performs a special sequence in enabling ls driver to switch: during the soft-start phase, the ls driver results disabled (ls=off) until the hs starts to switch. this avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output ( see figure 17 ). this particular feature of the device masks the ls turn-on only from the control loop point of view: protections are still allowed to turn-on t he ls mosfet in case of over voltage if needed. figure 17. low-side-less start-up comparison
L6714 output voltage monitor and protections 47/70 16 output voltage monitor and protections L6714 monitors through pin vsen the regulate d voltage in order to manage the ovp, uvp and pgood (when applicable) conditions. the device shows different thresholds when programming different operation mode (intel or amd, see table 10 ) but the behavior in response to a protection event is still the same as described below. protections are active also during soft-start ( see ?soft start? section ) while are masked during d-vid transitions with an additional 32 clock cycle delay after the transition has finished to avoid false triggering. 16.1 under voltage if the output voltage monitored by vsen drop s more than -750mv below the programmed reference for more than one clock period, L6714 turns off all mosfet and latches the condition: to recover it is required to cycle vcc or the outen pin. this is independent of the selected operative mode. 16.2 preliminary over voltage to provide a protection wh ile vcc is below the uvlo vcc threshold is fundamental to avoid damage to the cpu in case of failed hs mosfet. in fact, since the device is supplied from the 12v bus, it is basically ?blind? for any voltage below the turn-on threshold (uvlo vcc ). in order to give full protection to the load, a preliminary-ovp protection is provided while vcc is within uvlo vcc and uvlo ovp . this protection turns-on the low side mosfet as long as the fbr pin voltage is greater than 1.800v with a 350mv hysteresis. when set, the protection drives the ls mosfet with a gate-to-source voltage depending on the voltage applied to vccdrx and independently by the turn-on threshold across these pins (uvlo vccdr ). this protection depends also on the outen pin status as detailed in figure 18 . a simple way to provide protection to the output in all conditions when the device is off (then avoiding the unprotected red region in figure 18-left ) consists in supplying the controller through the 5v sb bus as shown in figure 18-right : 5v sb is always present before +12v and, in case of hs short, the ls mosfet is driven with 5v assuring a reliable protection of the load. preliminary ovp is always active before uvlo vcc for both intel and amd modes. figure 18. output voltage protections and typical principle connections vcc vccdr1 vccdr2 vccdr3 +12v +5v sb v cc uvlo ovp uvlo vcc preliminary ovp enabled fbr monitored no protection provided (outen = 1) programmable ovp vsen monitored (outen = 0) preliminary ovp fbr monitored
output voltage monitor and protections L6714 48/70 16.3 over voltage and programmable ovp once vcc crosses the turn-on threshold and the device is enabled (outen = 1), L6714 provides an over voltage pr otection: when the voltage se nsed by vsen overcomes the ovp threshold, the controller permanently switches on all the low-side mosfet and switches off all the high-side mosfet in order to protect the load. the osc/ fault pin is driven high (5v) and power supply or outen pin cycling is required to restart operations.the ovp threshold varies according to the operative mode selected ( see ta bl e 1 0 ). the ovp threshold can be also programmed through the ovp pin: leaving the pin floating, it is internally pulled-up and the o vp threshold is se t according to ta b l e 1 0 . connecting the ovp pin to sgnd through a resistor r ovp , the ovp threshold becomes the voltage present at the pin. since the ovp pin sources a constant i ovp = 12.5 a current( see table 10 ), the programmed voltage becomes: filter ovp pin with 100pf(max) vs. sgnd. 16.4 pgood (only for amd mode) it is an open-drain signal set free after the so ft-start sequence has finished. it is pulled low when the output voltage drops below -300mv of the programmed voltage. ovp th r ovp 12.5 a ? = r ovp ovp th 12.5 a ------------------- - = ?
L6714 maximum duty-cycle limitation 49/70 17 maximum duty-cycle limitation the device limits the maximum duty cycle and this value is not fixed but it depends on the delivered current given by the following relationship: from the previous relationships the maximum duty cycle results: if the desired output characteristic crosses the limited-d max maximum output voltage, the output resulting voltage will start to drop after the cross-point. in this case the output voltage starts to decrease following the resulting characteristic (dotted in figure 19 ) until uvp is detected or anyway until i droop =140 a. figure 19. maximum duty-cycle (left) and limited dmax output voltage (right) d max () 0.80 i droop 2.857k () ? 0.80 r sense r g --------------------- i out 2.857k ?? ?? ? == d max () 80% i droop 0 a = 40% i droop 140 a = ? ? ? = d max 40 % maximum duty cycle 80 % i droop = 140 a (i ocp = n x i ocpx ) i droop v out 0.40 v in limited d max output voltage 0.80 v in i ocp = n x i ocpx (i droop = 140 a) i out desired output char. uvp threshold resulting output char. limted-d max output char.
over current protection L6714 50/70 18 over current protection depending on the current reading method selected, the device limits the peak or the bottom of the inductor current entering in constant current until setting uvp as below explained. the over current threshold has to be programmed, by designing the rg resistors, to a safe value, in order to be sure that the device doesn't enter ocp during normal operation of the device. this value must take into consideration also the extra current needed during the dynamic vid transition i d-vid and, since the device reads across mosfet r dson or inductor dcr, the process spread and temperature variations of these sensing elements. moreover, since also the internal threshold spreads, the rg design has to consider the minimum value i octh(min) of the threshold as follow: where i ocpx is the current measured by the current reading circuitry when the device enters quasi-constant-current. i ocpx must be calculated starting from the corresponding output current value i out(ocp) as follow (i d-vid must also be considered when d-vid are implemented) considering that the device performs track & hold only for the ls sense mode: where i out(ocp) is still the output current value at which the de vice enters quasi-constant- current, i pp is the inductor current ripple in each phase i d-vid is the additional current required by d-vid (when applicable) and n the number of phases. in particular, since the device limits the peak or the valley of the inductor current (according to dac/cs_sel status), the ripple entity, when not negligible, impacts on the real oc threshold value and must be considered. rg i ocpx max () r sense max () ? i octh min () ----------------------------------------------------------------------- = i ocpx i out ocp () n -------------------------- - ? i pp 2 ------------ i dvid ? n ----------------- - + ? lowsidemosfetsense i out ocp () n -------------------------- - ? i pp 2 ------------ i dvid ? n ----------------- - ++ inductordcrsense ? ? ? ? ? ? ? =
L6714 over current protection 51/70 18.1 low side mosfet sense over current the device detects an over current condition for each phase when the current information i infox overcomes the fixed threshold of i octh (35 a typ,). when this happens, the device keeps the relative ls mosfet on, also skipping clock cycles, until the threshold is crossed back and i infox results being lower than the i octh threshold. after exiting the oc condition, the ls mosfet is turned off and the hs is turned on with a duty cycle driven by the pwm comparator. keeping the ls on, skipping clock cycles, causes the on-time subsequent to the exit from the oc condition, driven by the control loop, to increase. considerin g now that the device has a maximum on-time dependence with the delivered current given by the following relationship: where i out is the output current ( ) and t sw is the switching period (t sw =1/f sw ). this linear dependence has a value at zero load of 0.80t sw and at maximum current of 0.40t sw typical. when the current information i infox overcomes the fixed threshold of i octh (35 a typ), the device enters in quasi-constant-current operation: the low-side mosfet stays on until the current read becomes lower than i ocpx (i infox < i octh ) skipping clock cycles. the high side mosfet can be then turned on with a t on imposed by the control loop after the ls turn-off and the device works in the usual way until another ocp event is detected. this means that the average current delivered can slightly increase in quasi-constant- current operation since the current ripple increases. in fact, the on time increases due to the off time rise because of the current has to reach the i ocpx bottom. the worst-case condition is when the on time reaches its maximum value. when this happens, the device works in constant current and the output voltage decrease as the load increase. crossing the uvp threshold causes the device to latch ( figure 20 shows this working condition). it can be observed that the peak current (i peak ) is greater than i ocpx but it can be determined as follow: where v outmin is the uvp threshold, (inductor saturation must be considered). when that threshold is crossed, all mosfet are turned off and the device stops working. cycle the power supply or the outen pin to restart operation. the maximum average current during the constant-current behavior results: t on max () 0.80 t sw i droop 0 a = ? 0.40 t sw i droop 140 a = ? ? ? ? = i out i phasex = i peak i ocpx v in v out min () ? l ----------------------------------------- - t on max () ? + i ocpx v in v out min () ? l ----------------------------------------- - 0.40 t ? sw ? + == i max tot , ni max ? ni ocpx i peak i ocpx ? 2 ------------------------------------ + ?? ?? ? ==
over current protection L6714 52/70 in this particular situation, the switching frequency for each phase results reduced. the on time is the maximum allowed t on(max) while the off time depends on the application: figure 20. constant current the trans-conductance resistor rg can be desi gned considering that the device limits the bottom of the inductor current ripple and also considering the additional current delivered during the quasi-constant-current behavior as previously described in the worst case conditions. moreover, when designing d-vid compatible systems, the additional current due to the output filter charge during dynamic vid transitions must be considered. where t off l i peak i ocpx ? v out ------------------------------------ ? = f 1 t on max () t off + -------------------------------------------- - = v out 0.40 v in constant current (exploded) i ocp = 4 x i ocpx (i droop = 140 a) i out uvp threshold resulting out. char. i max,tot limted-t on char. droop effect quasi-const. current t on(max) t on(max) i ocpx i max i peak ls on skipping clock cycles t sw t sw rg i ocpx max () r sense max () ? i octh min () ----------------------------------------------------------------------- = i ocpx i out ocp () n -------------------------- - ? i pp 2 ------------ i dvid ? n ----------------- - + ? =
L6714 over current protection 53/70 18.2 inductor sense over current the device detects an over current when the ii nfox overcome the fixed threshold i octh . since the device always senses the current across the inductor, the i octh crossing will happen during the hs conduction time: as a co nsequence of ocp detection, the device will turn off the hs mosfet and turns on the lsmosfet of that phase until i infox re-cross the threshold or until the next clock cycle. this implies that the device limits the peak of the inductor current. in any case, the inductor current won't overcome the i ocpx value and this will represent the maximum peak value to consider in the oc design. the device works in constant-current, and the output voltage decreases as the load increase, until the output voltage reaches the uvp threshold. when this threshold is crossed, all mosfets are turned off and the device stops working. cycle the power supply or the outen pin to restart operation. the transconductance resistor rg can be designed considering that the device limits the inductor current ripple peak. moreover, when designing d-vid systems, the additional current due to the output filter charge during dynamic vid transitions must be considered. where rg i ocpx max () r sense max () ? i octh min () ----------------------------------------------------------------------- = i ocpx i out ocp () n -------------------------- - ? i pp 2 ------------ i dvid ? n ----------------- - ++ =
oscillator L6714 54/70 19 oscillator L6714 embeds four phase oscilla tor with optimized phase- shift (90o phase-sh ift) in order to reduce the input rms current and optimize the output filter definition. the internal oscillator generates the tria ngular waveform for the pwm charging and discharging with a constant current an internal capacitor. the switching frequency for each channel, f sw , is internally fixed at 150khz so that the resulting switching frequency at the load side results in being multiplied by n (number of phases). the current delivered to t he oscillator is typically 25 a (corresponding to the free running frequency f sw = 150khz) and it may be varied using an external resistor (r osc ) connected between the osc pin and sgnd or vcc (or a fixed voltage greater than 1.24v). since the osc pin is fixed at 1.24v, the frequency is varied proportionally to the current sunk (forced) from (into) the pin considering the internal gain of 6khz/ a. in particular connecting r osc to sgnd the frequency is increased (current is sunk from the pin), while connecting r osc to vcc = 12v the frequency is reduced (current is forced into the pin), according the following relationships: r osc vs. sgnd r osc vs. +12v when using the low-side mosfets current sense, the maximum programmable switching frequency per phase must be limited to 500khz to avoid current reading errors causing, as a consequence, current sharing errors. anyway, device power dissipation must be checked prior to design high switching frequency systems. f sw 150 khz () 1.240v r osc k ? () --------------------------- 6 khz a ---------- - ? + 150 khz () 7.422 10 3 ? r osc k ? () ------------------------------- r osc k ? () ? + f s w --------- -- == = hz -- ------ - 150 khz () 7.422 10 3 ? r osc k ? () ------------------------------- r osc k ? () ? + 7.422 10 3 ? f sw khz () 150 khz () ? ----------------------------------------------------------- - == k ? [] f sw 150 khz () 12v 1.240v ? r osc k ? () ----------------------------------- - 6 khz a ---------- - ? ? 150 khz () 6.456 10 4 ? r osc k ? () ------------------------------- ? r osc k ? () ? 1 5 ---- - == = 6 khz a ---------- - 150 khz () 6.456 10 4 ? r osc k ? () ------------------------------- ? r osc k ? () ? 6.456 10 4 ? 150 khz () f sw khz () ? ----------------------------------------------------------- - == k ? []
L6714 oscillator 55/70 figure 21. r osc vs. switching frequency 0 1000 2000 3000 4000 5000 6000 7000 25 50 75 100 125 150 fsw [khz] selected rosc [k ohms ] to +12v 0 50 100 150 200 250 300 350 400 450 500 550 150 250 350 450 550 650 750 850 950 1050 fsw [khz] programmed rosc [k ohms ] to sgnd
driver section L6714 56/70 20 driver section the integrated high-current drivers allow using different types of power mos (also multiple mos to reduce the equivalent r dson ), maintaining fast switching transition. the drivers for the high-side mosfets use bootx pins for supply and phasex pins for return. the drivers for the low-side mosfet s use vccdrx pin for supply and pgndx pin for return. a minimum voltage at vccdrx pin is required to start operations of the device. vccdrx pins must be connected together. the controller embodies a sophisticated anti-s hoot-through system to minimize low side body diode conduction time maintaining good ef ficiency saving the use of schottky diodes: when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2v, the low-side mosfet gate drive is suddenly applied. when the low- side mosfet turns off, the voltage at lgatex pin is sensed. when it drops below 1v, the high-side mosfet gate drive is suddenly applied. if the current flowing in the in ductor is negative, the source of high-side mosfet will never drop. to allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet doesn't drop, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. the bootx and vccdrx pins are separated from ic's power supply (vcc pin) as well as signal ground (sgnd pin) and power ground (pgndx pin) in order to maximize the switching noise immunity. the separated supply for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. several combination of supply can be chosen to optimize performanc e and efficiency of the application. power conversion input is also flexible; 5v, 12v bus or any bus that allows the conversion (see maximum duty cycle limitations) can be chosen freely.
L6714 system control loop compensation 57/70 21 system control loop compensation the control loop is composed by the current sharing control loop ( see figure 8 ) and the average current mode control loop. each loop gives, with a proper gain, the correction to the pwm in order to minimize the error in its regulation: the current sharing control loop equalize the currents in the inductors while the average current mode control loop fixes the output voltage equal to the reference programmed by vid. figure 22 shows the block diagram of the system control loop. the system control loop is reported in figure 23 . the current information i droop sourced by the droop pin flows into r fb implementing the dependence of the output voltage from the read current. figure 22. main control loop the system can be modeled with an equivalent single phase converter which only difference is the equivalent inductor l/n (where each phase has an l inductor).the control loop gain results (obtained opening the loop after the comp pin): l3 l2 l1 pwm3 pwm2 pwm1 4 / 5 v ref error amplifier comp fb z f (s) z fb (s) droop i droop c out r out 1 / 5 1 / 5 1 / 5 current sharing duty cycle correction i info1 i info3 i info2 l4 pwm4 1 / 5 i info4 g loop s () pwm z f s () r droop z p s () + () ?? z p s () z l s () + [] z f s () as () -------------- 1 1 as () ----------- - + ?? ?? r fb ? + ? ------------------------------------------------------------------------------------------------------------------------ - ? =
system control loop compensation L6714 58/70 where: r sense is the mosfet r dson or the inductor dcr depending on the sensing element selected; is the equivalent output resistance determined by the droop function; z p (s) is the impedance resulting by the parallel of the output capacitor (and its esr) and the applied load r o ; z f (s) is the compensation network impedance; z l (s) is the parallel of the n inductor impedance; a(s) is the erro r amplifier gain; is the pwm transfer function where ? v osc is the oscillator ramp amplitude and has a typical value of 4v. removing the dependence from the error amplifier gain, so assuming this gain high enough, and with further simplifications, the control loop gain results: the system control loop gain ( see figure 23 ) is designed in order to obtain a high dc gain to minimize static error and to cross the 0db axes with a constant -20db/dec slope with the desired crossover frequency t . neglecting the effect of z f (s), the transfer function has one zero and two poles; both the poles are fixed once the output filter is designed (lc filter resonance lc ) and the zero ( esr ) is fixed by esr and the droop resistance. figure 23. equivalent control loop block diagram (left) and bode diagram (right). to obtain the desired shape an r f - c f series network is considered for the z f (s) implementation. a zero at f = 1/r f c f is then introduced together with an integrator. this integrator minimizes the static error while placing the zero f in correspondence with the l- c resonance assures a simple -20db/dec shape of the gain. in fact, considering the usual value for the output filter, the lc resonance results to be at frequency lower than the above reported zero. r droop r sense rg --------------------- r fb ? = pwm 4 5 -- - v in ? v osc ------------------ - ? = g loop s () 4 5 -- - v in ? v osc --------------------- - z f s () r fb --------------- r o r droop + r o r l n ------- + ------------------------------------------- - 1s c o r droop //r o esr + () ?? + s 2 c o l n ----- ?? s l n r o ? --------------------- - c o esr ? c o r l n ------- ? ++ 1 + ? + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------ ??? ? ? = vid fb comp vsen fbr fbg 64k 64k 64k r f c f r fb droop pwm l / n esr c o r o d v out v out v out z f (s) z fb (s) remote buffer i droop db z f (s) g loop (s) k lc = f esr t r f [db]
L6714 system control loop compensation 59/70 compensation network can be simply designed placing f = lc and imposing the cross-over frequency t as desired obtaining (always considering that t might be not higher than 1/10th of the switching frequency f sw ): 21.1 compensation network guidelines the compensation network design assures to having system response according to the cross-over frequency selected and to the output filter considered: it is anyway possible to further fine-tune the compensation network modifying the bandwidth in order to get the best response of the system as follow ( see figure 24 ): increase r f to increase the system bandwidth accordingly; decrease r f to decrease the system bandwidth accordingly; increase c f to move f to low frequencies increasing as a consequence the system phase margin. having the fastest compensation network gives not the confidence to satisfy the requirements of the load: th e inductor still limits the maxi mum di/dt that the system can afford. in fact, when a load transient is applied, the best that the controller can do is to ?saturate? the duty cycle to its maximum (d max ) or minimum (0) value. the output voltage dv/dt is then limited by the inductor charge / discharge time and by the output capacitance. in particular, the most limiting transition corresponds to the load removal since the inductor results being discharged only by v out (while it is charged by d max v in -v out during a load appliance). referring to figure 24-left , further tuning the compensation network cannot give any improvements unless the output filter changes: only modifying the main inductors ot the output capacitance improves the system response. figure 24. r f -c f impact on bandwidth. r f r fb ? v osc ? v in ------------------------------------ - 5 4 -- - t l nr droop esr + () ? ---------------------------------------------------------- - ?? ? = c f c o l n --- - ? r f ----------------------- - = db z f (s) g loop (s) k lc = f esr t r f [db] r f c f
thermal monitor L6714 60/70 22 thermal monitor L6714 continuously senses the system temp erature through tm pin: depending on the voltage sensed by this pin, the device sets free the vr_fan pin as a warning and, after further temperature increase, also the vr_hot pin as an alarm condition. these signals can be used to give a boost to the system fan (vr_fan) and improve the vr cooling, or to initia te the cpu low power state (vr_hot) in order to reduce the current demand from the processor so reducing also the vr temperature. in a different manner, vr_fan can be used to initiate the cpu low power state so reducing the processor current requirements and vr_hot to reset the system in case of further dangerous temperature increase. thermal sensors is external to the pwm control ic since the controller is normally not located near the heat generating components: it is basically composed by a ntc resistor and a proper biasing resistor r tm . ntc must be connected as close as possible at the system hot-spot in order to be sure to control the hottest point of the vr. typical connection is reported in figure 25 that also shows how the trip point can be easily programmed by modifying the divider values in order to cross the vr_fan and vr_hot thresholds at the desired temperatures. both vr_hot and vr_fan are active high and open drain outputs. thermal monitoring output are enabled if vcc > uvlo vcc . figure 25. system thermal monitor typical connections. tm sense element (place remotely, near hot spot) +5v r tm tm voltage - ntc=3300/4250k 2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00 80 85 90 95 100 105 110 115 120 temperature [degc] tm voltage[v] rtm = 330 rtm = 390 rtm = 470
L6714 tolerance band (tob) definition 61/70 23 tolerance band (tob) definition output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. moreover, individual tolerance of the components also varies among designs: it is then possible to define a manufacturing tolerance band (tob manuf ) that defines the possible output voltage spread across the nominal load line characteristic. tob manuf can be sliced into different three main categories: controller tolerance, external current sense circuit tolerance and time constant matching error tolerance. all these parameters can be composed thanks to the rss analysis so that the manufacturing variation on tob results to be: output voltage ripple (v p = v pp /2) and temperature measurement error (v tc ) must be added to the manufacturing tob in order to get the system tolerance band as follow: all the component spreads and variations are usually considered at 3 . here follows an explanation on how to calculate these parameters for a reference L6714 application. 23.1 controller tolerance (tob controller) it can be further sliced as follow: reference tolerance. L6714 is trimmed during the production stage to ensure the output voltage to be within k vid = 0.5% (0.6% for amd dac) over temperature and line variations. in addition, the device automatically adds a -19mv offset (only for intel mode) avoiding the use of any external component. this offset is already included during the trimming process in order to avoid the use of any external circuit to generate this offsets and, moreover, avoiding the introduction of any further error to be considered in the tob calculation. current reading circuit. the device reads the current flowing across the mosfet rdson or the inductor dcr by using its dedi cated differential inputs. the current sourced by the vrd is then reproduced and sourced from the droop pin scaled down by a proper designed gain as follow: this current multiplied by the r fb resistor connected from fb pin vs. the load allows programming the droop function according to the selected r l /rg gain and r fb resistor. deviations in the current sourced due to errors in the current reading, impacts on the output voltage depending on the size of r fb resistor. the device is trimmed during the production stage in order to guarantee a maximum deviation of k ifb = 1 a from the nominal value. controller tolerance results then to be: tob manuf tob controller 2 tob currsense 2 tob tcmatching 2 ++ = tob tob manuf v p v tc ++ = i droop r sense rg --------------------- i out ? = tob controller vid 19mv ? () k vid ? [] 2 k idroop r fb ? () 2 + =
tolerance band (tob) definition L6714 62/70 23.2 ext. current sense circuit tolerance (tob currsense - inductor sense) it can be further sliced as follow: inductor dcr tolerance (k dcr ). variations in the inductor dcr impacts on the output voltage since the device reads a current that is different from the real current flowing into the sense element. as a resu lts, the controller will source a i droop current different from the nominal. the results will be an a vp different from the nominal in the same percentage as the dcr is different from the nominal. since all the sense elements results to be in parallel, the error related to the inductor dcr has to be divided by the number of phases (n). trans-conductance resistors tolerance (k rg ). variations in the rg resistors impacts in the current reading circuit gain and so impacts on the output voltage. the results will be an avp different from the nominal in the same percentage as the rg is different from the nominal. since all the sense elements results to be in parallel, and so the three current reading circuits, the error related to the rg resistors has to be divided by the number of phases (n). ntc initial accuracy (k ntc_0 ). variations in the nt c nominal value at room temperature used for the thermal compensation impacts on the avp in the same percentage as before. in addition, the benefit of the division by the number of phases n cannot be applied in this case. ntc temperature accuracy (k ntc ). ntc variations from room to hot also impacts on the output voltage positioning. the impact is bigger as big is the temperature variation from room to hot ( ? t). all these parameters impacts the avp, so they must be weighted on the maximum voltage swing from zero load up to the maximum electrical current (v avp ). total error from external current sense circuit results: tob currsense v avp 2 k dcr 2 n ------------- - k rg 2 n --------- k ntc0 2 ? tk ntc ?? dcr -------------------------------------- - ?? ?? 2 ++ + ? =
L6714 tolerance band (tob) definition 63/70 23.3 time constant matching er ror tolerance (tob tcmatching) inductance and capacitance tolerance (k l , k c ). variations in the inductance value and in the value of the capacitor used for the time constant matching causes over/under shoots after a load transient appliance. this impacts the output voltage and then the tob. since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divi ded by the number of phases (n). capacitance temperature variations (k ct ). the capacitor used for time constant matching also vary with temperature ( ? t c ) impacting on the output voltage transients ad before. since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be di vided by the number of phases (n). all these parameters impact the dynamic avp, so they must be weighted on the maximum dynamic voltage swing (i dyn ). total error due to time constant mismatch results: 23.4 temperature me asurement error (v tc ) error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat. the measurement error ( te m p ) must be multiplied by the copper temp coefficient ( ) and compared with the sensing resistance (r sense ): this percentage affects the avp voltage as follow: tob tcmatching v avpdyn 2 k l 2 k c 2 k ct ? tc ? () ++ n --------------------------------------------------------- ? = v tc temp ? r sense -------------------------- v avp ? =
layout guidelines L6714 64/70 24 layout guidelines since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. a good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection be tween signal and power ground can optimize the performance of the control loops. two kind of critical components and connections have to be considered when layouting a vrm based on L6714: power components and connections and small signal components connections. 24.1 power components and connections these are the components and connections where switching and high continuous current flows from the input to the load. the first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage sp ikes (emi and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. the critical components, i.e. the power transistors, must be close one to the other. the use of multi-layer printed circuit board is recommended. figure 26 shows the details of the power connections involved and the current loops. the input capacitance (c in ), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. low esr and esl capacitors are preferred, mlcc are suggested to be connected near the hs drain. use proper vias number when power traces have to move between different planes on the pcb in order to reduce both parasitic resistance and inductance. moreover, reproducing the same high-current trac e on more than one pcb layer will reduce the parasitic resistance associated to that connection. connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. gate traces must be sized according to the driver rms current delivered to the power mosfet. the device robustness allows managing applications with the power section far from the controller without losing performances. external gate resistors help the device to dissipate power resulting in a general cooling of the device. when driving multiple mosfets in parallel, it is suggested to use one resistor for each mosfet.
L6714 layout guidelines 65/70 24.2 small signal components and connections these are small signal components and connecti ons to critical nodes of the application as well as bypass capacitors for the device supply ( see figure 26 ). locate the bypass capacitor (vcc, vccdrx and bootstrap capacitor) close to the device and refer sensible components such as frequency set-up resistor r osc , offset resistor r offset and ovp resistor r ovp to sgnd. star grounding is suggested: connect sgnd to pgnd plane in a single point to avoid that drops due to the high current delivered causes errors in the device behavior. vsen pin filtered vs. sgnd help s in reducing noise injecti on into device and outen pin filtered vs. sgnd helps in reducing false trip due to coupled noise: take care in routing driving net for this pin in order to minimize coupled noise. warning: boot capacitor extra charge. systems that do not use schottky diodes might show big negative spikes on the phase pin. this spike can be limited as well as the positive spike but has an additional consequence: it causes the bootstrap capacitor to be over-charged. this extra-charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also causing device failures. it is then suggested in this cases to limit this extra- charge by adding a small resistor in series to the boot diode (one resistor can be enough for all the three diodes if placed upstream the diode anode, see figure 26 ) and by using standard and low-capacitive diodes. figure 26. power connections and related connections layout (same for all phases). remote buffer connection must be routed as parallel nets from the fbg/fbr pins to the load in order to avoid the pick-up of any common mode noise. connecting these pins in points far from the load will cause a non-optimum load regulation, in creasing output tolerance. locate current reading components close to the device. the pcb traces connecting the reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up of any common mode noise. it's also important to avoid any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements. symmetrical layout is also suggested. small filtering capacitor can be added, near the controller, between v out and sgnd, on the csx- line when reading across inductor to allow higher layout flexibility. l c in v in ugatex phasex lgatex pgndx load bootx phasex vcc sgnd +vcc c boot l c in v in load to limit c boot extra-charge
embedding L6714 - based vr L6714 66/70 25 embedding L6714 - based vr when embedding the vrd into the application, additional care must be taken since the whole vrd is a switching dc/dc regulator and th e most common system in which it has to work is a digital system such as mb or similar. in fact, latest mb has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the vrd can affect data integrity if not following additional layout guidelines. few easy points must be considered mainly w hen routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): keep safe guarding distance between high current switching vrd traces and data buses, especially if high-speed data bus to minimize noise coupling. keep safe guard distance or f ilter properly when routing bias traces for i/o sub-systems that must walk near the vrd. possible causes of noise can be located in the phase c onnections, mosfet gate drive and input voltage path (from input bulk capaci tors and hs drain). also pgnd connections must be considered if not insisting on a power ground plane. these connections must be carefully kept far away from noise-sensitive data bus. since the generated noise is mainly due to the switching activity of the vrm, noise emissions depend on how fast the current switches. to reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the hs gate resistor and the phase snuber network.
L6714 package mechanical data 67/70 26 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com .
package mechanical data L6714 68/70 table 13. tqfp64 mechanical data dim. mm. inch min typ max min typ max a 1.20 0.0472 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1.05 0.0374 0.0393 0.0413 b 0.17 0.22 0.27 0.0066 0.0086 0.0086 c 0.09 0.20 0.0035 0.0078 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d2 3.50 6.10 0.1378 0.2402 d3 7.50 0.295 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e2 3.50 6.10 0.1378 0.2402 e3 7.50 0.295 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0393 k 0 3.5 7 0 3.5 7 ccc 0.080 0.0031 figure 27. package dimensions
L6714 revision history 69/70 27 revision history table 14. revision history date revision changes 16-mar-2006 1 initial release. 02-aug-2006 2 updated k idroop , k ioffset values in table 4: electrical characteristics on page 14 . 07-nov-2006 3 updated d2 and e2 exposed tab measures in ta b l e 1 3 : tqfp64 mechanical data .
revision history L6714 70/70 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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